Power management implementation and verification are critical considerations in any integrated circuit design process. As power consumption in integrated circuits increases, chip reliability, quality and productivity are negatively impacted. The challenges of high power consumption require the introduction of low power reduction techniques, solutions and tools as integral parts of integrated circuit design implementation and verification flow processes.
Design implementation and verification flow processes often include the use of assertions to check design behavior and measure functional coverage. Assertions may be used to check the required and/or expected behavior of a design throughout the simulation process. Additionally, assertions are typically used to look for forbidden behavior or expected outcomes and check the functional coverage of a design. However, it is often unclear at what stage of the design process the assertions should be written and who should write them. Furthermore, generating assertions manually to monitor and check design behavior is frequently a complex, time-consuming and error-prone task.